The following logic gates can be made (for one level deep logic at least, they use up less space that a x4 logic gate chip):
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TTL chip technology uses a transistor and resistor combination, and CMOS (Complementary MOS) uses NPN and PNP apposite each other linking between +V (3-15V) and 0V. Basically when one is on, the other is off, thus using less power. As you only use power when switching the transistor not burn up power on the resistor all the time. That's why they are used in clock circuit as the batteries last longer.
Why can't they make chips using Diodes, NP only???? This would take up less space and presumably use less power. One point is 'Diode-Clamp' technology can't form one type of logic gate. Another is that the drop of 0.6V accumulates with additional gates. Most processors use big addressing lines that require multiple levels of logic gate. But at a certain depth you could convert back to Transistors. Perhaps the chip might be more susceptible to static damage? I don't know if this is true.
Probably you would need at least 14.5 Volt to allow for bigger voltage drops. PC's only have 5V and 12V. This could link into CMOS (max. 15V). Chips are formed of four or more layers: P, N, P, and Resistor, so a normal chip screen could be used mixing Diodes and Transistors. The unwanted layers are simply etched away.